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Introduction to Hardware/Software Codesign
www.diva-portal.org
von S Ha · · Zitiert von: 9 — ... Handbook of Hardware/Software Codesign / [ed] Soonhoi Ha, Jürgen Teich, Springer Netherlands, 2017Chapter in book (Refereed) ... › record
Search | arXiv e-print repository
arxiv.org
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. Authors: Bernhard Schmidt, Daniel Ziener, Jürgen Teich, ...
Andreas Weichslgartner Stefan Wildermann Jürgen Teich …
content.e-bookshelf.de
WebJürgen Teich, Erlangen, Germany Debdeep Mukhopadhyay, Kharagpur, India. Twilight zone of Moore’s law is affecting computer architecture design like never before. The …
[ ] A Design-Time/Run-Time Application Mapping Methodology...
arxiv.org
Authors:Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich. (Submitted on 16 Nov 2017). Abstract: Executing ...
DATE Abstracts | DATE 2016
past.date-conference.com
Chairs: Jörg Henkel, Karlsruhe Institute of Technology, DE Jürgen Teich, Erlangen-Nuremberg U, DE . A Landscape of the New Dark Silicon Design Regime Michael B. Taylor . The rise of dark silicon is driving a new class of architectural techniques that "spend" area to "buy" energy efficiency.
[ ] Adaptive Predictive Power Management for Mobile LTE...
arxiv.org
Authors:Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich. (Submitted on 5 Jul 2019). Abstract: ...
Efficient Table-based Function Approximation on FPGAs using ...arXiv
arxiv.org
von C Pradhan · — ... Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. Authors:Chetana Pradhan, Martin Letras, Jürgen Teich. › cs
TIK - Report No. 16 Abstract
www.handshake.de
System-Level Synthesis Using Evolutionary Algorithms Tobias Blickle, Jürgen Teich, Lothar Thiele, April 1996, TIK-Report No. 16 available as PostScript
[ ] Isolation-Aware Timing Analysis and Design Space...
arxiv.org
Authors:Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich. (Submitted on 31 May (v1), last revised 24 Jun (this version, v3)).
Unbounded safety verification for hardware using software ...
www.cs.ox.ac.uk
2016 Design‚ Automation & Test in Europe Conference & Exhibition‚ DATE 2016‚ Dresden‚ Germany‚ March 14–18‚ Editor. Luca Fanucci and Jürgen Teich. › publicati...
[ ] Secure Boot from Non-Volatile Memory for Programmable...
arxiv.org
... Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich · Download ...
[ ] Optimizing Scrubbing by Netlist Analysis for FPGA...
arxiv.org
Authors:Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner. (Submitted on 25 Jul 2017). Abstract: Existing scrubbing techniques ...
[ ] Raw Filtering of JSON Data on FPGAs
arxiv.org
von T Hahn · — Raw Filtering of JSON Data on FPGAs. Authors:Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich · Download PDF. Abstract: Many Big ... › cs
[cs ] Optimal Free-Space Management and Routing-Conscious...
arxiv.org
Authors:Ali Ahmadinia, Christophe Bobda, Sandor Fekete, Juergen Teich, Jan van der Veen. (Submitted on 18 Jun (v1), last revised 28 Sep (this ...
[cs ] DyNoC: A Dynamic Infrastructure for Communication in...
arxiv.org
Authors:Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Juergen Teich, Sandor P. Fekete, Jan van der Veen · Download PDF. Abstract: A ...
[cs ] Higher-Dimensional Packing with Order Constraints
arxiv.org
Title:Higher-Dimensional Packing with Order Constraints. Authors:Sandor P. Fekete, Ekkehard Koehler, Juergen Teich · Download PDF.
[cs ] A Practical Approach for Circuit Routing on Dynamic...
arxiv.org
Authors:Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Juergen Teich, Sandor P. Fekete, Jan van der Veen. (Submitted on 24 Mar ...
[ ] Symbolic Loop Compilation for Tightly Coupled Processor...
arxiv.org
· Title:Symbolic Loop Compilation for Tightly Coupled Processor Arrays. Authors: Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich.
[ ] Massively Parallel Processor Architectures for...
arxiv.org
Authors: Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich. (Submitted on 12 May 2014). Abstract: We present a class of massively parallel processor ...
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